1. Field of the Invention
The present invention relates generally to semiconductor structures and manufacturing. More particularly the invention relates to the formation of polycrystalline silicon gate electrodes for metal-oxide-semiconductor field effect transistors (MOSFETs).
2. Background
Advances in semiconductor manufacturing technology have led to the integration of tens, and more recently, hundreds of millions of circuit elements, such as transistors, on a single integrated circuit (IC). In order to achieve such increases in density, not only have interconnect line widths become smaller, but so have the dimensions of metal-oxide-semiconductor field effect transistors.
MOSFETs are also sometimes referred to as insulated gate field effect transistors (IGFETs). Most commonly, these devices are referred to simply as FETS, and are so referred to in this disclosure.
Transistor scaling typically involves more than just the linear reduction of the FET width and length. For example, both source/drain (S/D) junction depth and gate insulator thickness are also typically reduced in order to produce a FET with the desired electrical characteristics.
As is well known, the gate electrode of a FET is commonly formed from a patterned layer of polycrystalline silicon. Polycrystalline silicon is also referred to as polysilicon. These polysilicon gate electrodes are commonly doped such that the gate electrodes of n-channel FETs (NFETS) are n-type, and the gate electrodes of p-channel FETs (PFETs) are p-type.
Since doped polysilicon is a semiconductor material, it tends to experience the formation of a depletion region adjacent to the interface between the gate electrode and the gate insulator (also referred to as the gate dielectric) when a voltage is applied to the gate electrode. As transistor scaling has substantially reduced the thickness of the gate insulator layer, the width of the depletion region in the doped polysilicon gate electrode has come to play a more significant role in determining the electrical characteristics of the FET. Unfortunately, the occurrence of this depletion region in the gate electrode tends to limit transistor performance.
What is needed is a gate electrode structure that substantially overcomes the problems associated with polysilicon depletion layers, and methods of making such a gate electrode structure.
Briefly, a method of fabricating a FET having a gate electrode with reduced susceptibility to the carrier depletion effect, includes increasing the amount of n-type dopant in the gate electrode of an n-channel FET.
In one embodiment of the present invention, an integrated circuit including n-channel and p-channel FETs is produced with increased n-type doping in the n-channel FET gate electrodes without the use of additional photomasking operations.